/*
 Level-sensitive sequential UDP test.
*/

module top ;

 wire q;
 reg ck, data;

 latch l (q, ck, data);

 initial begin
  $display ("q\tl.q\tclock\tdata\n---------------------------------");
  $strobe  ("%b\t%b\t%b\t%b", q, l.q, ck, data);
  data = 1;
  ck = 0;
  #1;
  ck = 1;  //here thw UDP will switch to 1
  data = 0;
  #1;
  ck = 0;
  #1;
 end //initial
endmodule

primitive latch (q, clock, data);
output q;
reg q;
input clock, data;
table
// clock data   q   q+
     0     1  : ? : 1 ;
     0     0  : ? : 0 ;
     1     ?  : ? : - ;
endtable
endprimitive
